netX 6/51/52/100/500 Network controller for Real-Time Ethernet and fieldbus master and slaves with display controller

netX6:

The netX 6 is a member of Hilscher’s family of highly integrated network controllers with a new system architecture optimized for communication and maximum data throughput. Connected through its integrated dual-port memory with up to 32-bit bus width, the netX 6 can be used in conjunction with nearly any 16/32-bit CPU and provides the complete scope of industrial communication from fieldbus systems up to the Real-Time Ethernet systems. The integrated 32-Bit RISC Controller executes the time critical low layer functions of the communication protocol and reduce the necessary bandwidth between netX 6 and Host CPU. Extensive peripheral functions, serial interfaces, such as UART, USB, SPI, I²C allow a large scope of applications. The identical set of controllers of the two communication channels are structured on two levels. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. For Ethernet the PHYs are integrated which means that the external circuit for Ethernet is reduced to passive componets: transformer and RC components. The Medium Access Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into Byte depictions.The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. Large data amounts are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a dual port memory available for status information. Alternatively a triple buffer logic is implemented for a conflict free data exchange which always gives the address of the next free buffer. With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations on one chip – an absolutely new feature in industrial communication technology.

netX51/52:

Real-time Ethernet systems are successfully used and further developed in many applications. The demands made on the resources and functionalities of network controllers are therefore increasing. The network controllers netX 51 / 52 bank on the further developed netX 50 communications architecture, which features considerably more internal storage capacity and additional function units. The netX 51 hardware is compatible with the netX 50. The netX 52 contains the same silicon, but dispenses with an external memory bus, and due to its smaller housing, is more cost-effective. These three components are thus optimized for designing modular or compact slaves, or as a Real-time Ethernet controller on a high-performing CPU. Furthermore, the new PHYs manufactured by Renesas are applied, ensuring faster throughput times and expanded diagnosis properties. Through the internal memory for more than 670 KByte, it is possible to build together with a QSPI Flash very compact solutions with twice the performance of netX 50. For processing the fast IOs, the application is provided with a second RISC CPU. It works in parallel to ARM and significantly relieves the demands made on the ARM software via short bus cycle times. A third Ethernet interface for connecting a PC for diagnosis and configuration purposes is implemented. Alternatively, it can also be used for connecting the netX to a host CPU. The netX then behaves like a PHY on this MII interface. Some Real-time Ethernet systems use the CANopen object models. This results in the task of connecting CAN as the „legacy“ network to the Real-time Ethernet system. Up to now, that entailed using an expensive netX 100 controller, with its three communication channels. As an alternative, a dedicated controller is now available. With this possibility, the netX 51 / 52 is so much more than just a Real-time Ethernet interface chip equipped with a dual-port memory.

netX100/500:

The netX is a highly integrated network controller with a new system architecture optimized for communication and maximum data throughput. Based on the 32-bit CPU ARM 926EJ-S cycled at 200 MHz, it possesses a memory management unit, caches, DSP and Java extensions. The internal memory of 144 KByte RAM and 32 KByte ROM that contains the boot loader is sufficient for smaller applications whereas for Windows CE and Linux it is supplemented with the 32-bit Memory Controller memory externally with SDRAM, SRAM or FLASH. The connection to a primary host is carried out via the dual-port memory interface, which is configurable for stand-alone applications also as a 16-bit extension bus. Comprehensive peripheral functions, serial interfaces such as UART, USB, SPI, I²C as well as the integrated graphic controller permit a wide spectrum of applications. Yet, it is the central data switch and the three four configurable communication channels with their own intelligence that is the main characteristic of the netX as a "high end" network controller.
The data switch connects via five data paths to the ARM CPU and the communication, graphic and host controllers with the memory or the peripheral units. In this way the controllers transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles. The controllers of the four communication channels are structured on two levels and are identical to each other. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. Two channels possess an additional integrated PHY for Ethernet. The Medium Access Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into byte depictions. The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. These are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a dual-port memory available for status information or as local data image. With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations and can synchronize them independently of the reaction time of the CPU – an absolutely new feature in industrial communication technology.