ET1810, ET1811, ET1812 | EtherCAT IP core for Altera® FPGAs
The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (field programmable gate array, an integrated circuit containing programmable logical components). The EtherCAT functionality is freely configurable. The IP core can be combined with your own FPGA designs or integrated into system-on-chips (SoCs) with soft-core processors or hard processor systems via Avalon® or AMBA® AXI™ interfaces. The physical interfaces and internal functions, such as the number of FMMUs and SYNC managers and the size of the DPRAM, are configurable. The process data interface (PDI) and the distributed clocks are also configurable. The functions are compatible with the EtherCAT specification and the EtherCAT ASIC ET1100.
The ET1811 quantity-based node-locked license offers small-batch manufacturers and development service providers in particular the option to enter the world of EtherCAT development with a low initial investment. The ET1811 one-time kick-off charge and the license fees for 1,000 ET1811-1000 devices are required for the development of an EtherCAT device. The license fees for 1,000 devices must each be paid in advance.
Development service providers only require the ET1811 basic license; the ET1811-0030 system integrator OEM license is required for each customer implementation. The quantity-based license (ET1811-1000) is purchased by the end customer.
The license includes one year of maintenance and updates to ensure that you always have access to the latest developments and improvements.
The EtherCAT IP core can be tested once, with the test period lasting three months, free of charge. The evaluation license has the following pre-requisites: free membership of the EtherCAT Technology Group with an existing Vendor ID.
| Configurable features: | ET1810, ET1811, ET1812 |
|---|---|
| PHY interface | 1…4 MII/RGMII/RMII ports |
| FMMUs | 0…16 |
| SYNC manager | 0…16 |
| DPRAM | 0…60 KB |
| Distributed clocks | 0…4 SYNC outputs, 0…4 latch inputs (32/64 bit) |
| Process data interfaces | PDI0: 32 bit digital I/O, SPI slave, 8/16/32 bit asynchrones µC-Interface, Avalon interface, AMBA AXI4 interface. PDI1: 32 bit digital I/O, SPI slave, Avalon interface, AMBA AXI4 interface. 64 bit general purpose I/O |
The EtherCAT Altera® IP core can be used with the following FPGAs:
- AgilexTM 3, Agilex 5, Agilex 7
- Arria® V, Arria V GZ, Arria 10
- Cyclone® IV E+GX, Cyclone V, Cyclone V SoC, Cyclone 10 LP+GX
- MAX®10
- Stratix® IV, Stratix V, Stratix 10
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